1. Field of the Invention
The present invention relates to an interleaving AD conversion type waveform digitizer. In particular, the present invention relates to a correction means for detecting a measurement error caused by a phase error of a sampling timing in interleaving AD conversion so as to correct the detected measurement error.
2. Related Art
An N-way interleaving AD conversion type waveform digitizer can increase an apparent sampling rate by using N A/D converters. This type of waveform digitizer is required to perform sampling at precise timings.
FIG. 7 shows a structure of a conventional digitizer 200 used in a testing apparatus for testing an electronic device. The digitizer 200 includes four A/D converters (ADCs) 110, four clocks 112, an interleaving unit 114 and a digital filter 116. Each A/D converter 110 samples an analog signal output from the electronic device based on timings supplied to the associated clock 112, thereby converting the analog signal to a digital signal. The interleaving unit 114 generates a data sequence obtained by arranging the digital signals converted by the four A/D converters 110 in a predetermined order. The digital filter 116 multiplies the data sequence generated by the interleaving unit 114 by a correction coefficient based on a predetermined impulse response function. The digital filter 116 removes a predetermined frequency component from the data sequence by the above multiplication. Then, the digital filter 116 outputs the data sequence multiplied by the correction coefficient to a determination unit of the testing apparatus. The determination unit determines based on the data sequence multiplied by the correction coefficient whether or not the electronic device is defective.
The four A/D converters have to be adjusted in phase in such a manner that the sampling timings thereof are arranged at constant phase intervals. In a case where the sampling timings of the respective A/D converters contain phase errors, the interleaving unit 114 and the digital filter 116 process the digital data output from the respective A/D converters while assuming that that digital data were obtained by sampling at constant intervals. As a result, the data sequence output from the digital filter 116 also contains an error with respect to the analog signal output from the electronic device. Therefore, the determination unit cannot precisely determine whether or not the electronic device under test is defective.
According to the conventional technique, the phase intervals between the sampling timings of the A/D converters were adjusted to be constant, as described above. On the other hand, the sampling characteristics of the A/D converter are affected by variation of parts in the A/D converter, the environmental temperature, the change with time, the fluctuation of supply voltage, thus affecting the sampling at constant intervals that is intended. Moreover, it was very difficult to supply clocks to a plurality of A/D converters so as to realize the sampling timings at constant phase intervals. These factors cause the fluctuation of the sampling timing from ideal sampling timing. This made it difficult to precisely reproduce the analog signal output from the electronic device. Thus, it became difficult to precisely determine whether or not the electronic device is defective.
Therefore, it is an object of the present invention to provide an AD conversion type digitizer and a semiconductor testing apparatus that can correct phase shifts of sampling between a plurality of A/D converters so as to precisely reproduce an analog signal. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
In order to achieve the above object, according to the first aspect of the present invention, a digitizer for converting an analog signal output from an electronic device to a digital signal, includes: an A/D converter operable to sequentially convert the analog signal output from the electronic device to a digital signal at predetermined time intervals; a digital filter operable to output a corrected signal obtained by multiplying the digital signal converted by the A/D converter by a correction coefficient; and a digital filter operable to output a corrected signal obtained by multiplying the digital signal converted by the A/D converter by a correction coefficient based on a phase error between an ideal sampling timing at which the A/D converter is to sample the analog signal and an actual timing at which the A/D converter sampled the analog signal.
The digital filter may have an impulse response function given thereto for calculating the correction coefficient, and the digital filter may output the corrected signal obtained by calculating convolution of the correction coefficient, that is a value of the impulse response function corresponding to a timing away from the ideal sampling timing by the phase error, and values of the digital signal.
According to the second aspect of the present invention, a digitizer for converting an analog signal output from an electronic device to a digital signal, includes: N A/D converters operable to convert the analog signal output from the electronic device to digital signals at different sampling timings by turns, N being an integer equal to or larger than 2; and N digital filters operable to output corrected signals, each of the corrected signals being obtained by multiplying one of the digital signals output from an associated one of the N A/D converters by a correction coefficient based on a phase error between an ideal sampling timing at which the associated A/D converter is to sample the analog signal and an actual sampling timing at which the associated A/D converter sampled the analog signal.
Each of the N digital filters may include a memory in which an impulse response function for calculating the correction coefficient is stored, and the N digital filters may output the corrected signals each obtained by calculating convolution of the correction coefficient, that is a value of the impulse response function corresponding to a timing away from the ideal sampling timing by the phase error of the associated A/D converter, and values of the digital signal converted by the associated A/D converter. In addition, the memory may store the impulse response function based on gain characteristics of the associated A/D converter. Moreover, the memory may store the impulse response function based on frequency characteristics of the associated A/D converter.
Each of the N digital filters may include a memory for storing as the correction coefficient a value of an impulse response function of the digital filter at the actual sampling timing of the associated A/D converter, and the N digital filters may output the corrected signals each obtained by calculation of convolution of values of the digital signal converted by the associated A/D converter and the correction coefficient. In addition, the memory may store the correction coefficient based on gain characteristics of the associated A/D converter. Moreover, the memory may store the correction coefficient based on frequency characteristics of the associated A/D converter.
The digitizer may further include an interleaving unit operable to generate a data sequence obtained by arranging the corrected signals respectively output from the N digital filters in a predetermined order. Moreover, the digitizer may further include a decimation data generation unit operable to calculate a sum of the corrected signals respectively output from the plurality of digital filers to generate decimation data, wherein each of the N digital filters multiplies the digital signal output from the associated A/D converter by the correction coefficient based on: a phase error between the ideal sampling timing at which the associated A/D converter is to sample the analog signal and the actual sampling timing at which the associated A/D converter sampled the analog signal; and a phase difference between the ideal sampling timing of the associated A/D converter and an ideal sampling timing of one of the N A/D converters that is used as a reference A/D converter.
Each of the N digital filters may include a memory for storing a plurality of correction coefficients obtained by decomposing a predetermined impulse response function by a polyphase decomposition and multiplying results of the polyphase decomposition by a coefficient based on the phase error, and the N digital filters may output the corrected signals obtained by calculation of convolution of the plurality of correction coefficients and the digital signals. Moreover, the memory of each of the N digital filters may store, as the plurality of correction coefficients, values obtained by multiplying values of the impulse response function at the ideal sampling timings of the associated A/D converter by the coefficient based on the phase error. Furthermore, the memory of each of the N digital filters may store the plurality of correction coefficients based on a function obtained by moving the impulse response function on a time axis by a difference between a phase of the ideal sampling timing of the associated A/D converter and a phase of the ideal sampling timing of the reference A/D converter, and the phase error.
According to the third aspect of the present invention, a digitizer for converting an analog signal output from an electronic device to a digital signal, includes: N A/D converters operable to convert the analog signal output from the electronic device to digital signals at different sampling timings by turns, N being an integer equal to or larger than 2; a first interleaving unit operable to generate a first data sequence obtained by arranging the digital signals converted by the N A/D converters in a predetermined order to output the first data sequence; N digital filters operable to receive the first data sequence output from the first interleaving unit, to calculate convolution of correction coefficients based on phase errors between ideal sampling timings at which the N A/D converters are to sample the analog signal and actual sampling timings at which the N A/D converters sampled the analog signal and the first data sequence so that each of the N digital filters generate and output decimation data containing less number of data units than data units in the first data sequence; and a second interleaving unit operable to generate a second data sequence obtained by arranging the data units in the decimation data output from each of the N digital filters in a predetermined order.
In the third aspect of the present invention, the N digital filters may include memories operable to store impulse response functions for calculating the correction coefficients, and may output signals obtained by convolution of values of the impulse response functions corresponding to timings away from the ideal sampling timings by the phase errors of associated A/D converters and values of the digital signals converted by the associated A/D converters, respectively.
According to the fourth aspect of the present invention, a testing apparatus for testing an electronic device, includes: a pattern generator operable to generate a pattern signal and an expected-value signal; a waveform shaping unit operable to shape a waveform of the pattern signal generated by the pattern generator; a device contact unit, onto which the electronic device is to be placed, operable to supply the pattern signal shaped by the waveform shaping unit to the electronic device and to receive an analog signal output from the electronic device; a digitizer operable to convert the analog signal output from the electronic device to a digital signal; and a determination unit operable to determine based on the expected-value signal output from the pattern generator and a signal output from the digitizer whether or not the electronic device is defective, wherein the digitizer includes: an A/D converter operable to sequentially convert the analog signal output from the electronic device to digital signals at predetermined intervals; and a digital filter operable to output corrected signals calculated by multiplying the digital signals converted by the A/D converter by a correction coefficient, and the digital filer multiplies the digital signals by the correction coefficient based on a phase error between ideal sampling timings at which the A/D converter is to sample the analog signal and sampling timings at which the A/D converter sampled the analog signal.
According to the fifth aspect of the present invention, a testing apparatus for testing an electronic device, includes: a pattern generator operable to generate a pattern signal and an expected-value signal; a waveform shaping unit operable to shape a waveform of the pattern signal generated by the pattern generator; a device contact unit, onto which the electronic device is to be placed, operable to supply the pattern signal shaped by the waveform shaping unit to the electronic device and to receive an analog signal output from the electronic device; a digitizer operable to convert the analog signal output from the electronic device to a digital signal; and a determination unit operable to determine based on the expected-value signal output from the pattern generator and a signal output from the digitizer whether or not the electronic device is defective, wherein the digitizer includes: N A/D converters operable to convert the analog signal output from the electronic device to digital signals at different sampling timings, N being an integer equal to or larger than 2; and N digital filters operable to output corrected signals obtained by multiplying the digital signals output from the N A/D converters by correction coefficients, and wherein the N digital filters multiply the digital signals converted by associated A/D converters by the correction coefficients based on phase errors between ideal sampling timings at which the associated A/D converters are to sample the analog signal and sampling timings at which the N A/D converters sampled the analog signal.
The digitizer may further include a decimation data generation unit operable to calculate a sum of the corrected signals respectively output from the plurality of digital filters to generate decimation data, wherein the N digital filters output the corrected signals obtained by multiplying the digital signals converted by the associated A/D converters by the correction coefficients based on: phase errors between the ideal sampling timings at which the associated A/D converters are to sample the analog signal and the actual sampling timing at which the N A/D converters sampled the analog signal; and phase differences between the ideal sampling timings of the associated A/D converters and ideal sampling timings of one of the N A/D converters that is used as a reference.
According to the sixth aspect of the present invention, a testing apparatus for testing an electronic device includes: a pattern generator operable to generate a pattern signal and an expected-value signal; a waveform shaping unit operable to shape a waveform of the pattern signal generated by the pattern generator; a device contact unit, onto which the electronic device is to be placed, operable to supply the pattern signal shaped by the waveform shaping unit to the electronic device and to receive an analog signal output from the electronic device; a digitizer operable to convert the analog signal output from the electronic device to a digital signal; and a determination unit operable to determine based on the expected-value signal output from the pattern generator and a signal output from the digitizer whether or not the electronic device is defective, wherein the digitizer includes: N A/D converters operable to convert the analog signal output from the electronic device to digital signals at different sampling timings by turns, N being an integer equal to or larger than 2; a first interleaving unit operable to generate and output a first data sequence obtained by arranging the digital signals converted by the N A/D converters in a predetermined order; N digital filters operable to receive the first data sequence output from the first interleaving unit and to calculate convolution of correction coefficients, based on phase errors between ideal sampling timings at which the N A/D converters are to sample the analog signal and actual sampling timings at which the N A/D converters sampled the analog signal, and the first data sequence to generate and output decimation data, the decimation data of each of the N digital filters containing less number of data units than data units in the first data sequence; and a second interleaving unit operable to generate a second data sequence obtained by arranging the data units in the decimation data output from the N digital filters in a predetermined order.
The summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above.